The present invention relates generally to semiconductor device manufacturing and, more particularly, to integrated circuit test optimization using an adaptive test pattern sampling algorithm.
Semiconductor devices are typically fabricated in large lots on semiconductor wafers. The fabrication process includes various steps such as, for example, deposition, lithography, etching, sputtering, and other techniques known to those skilled in the art. As with any other manufacturing process, defects inevitably arise during semiconductor manufacturing. These defects must be detected by the manufacturer before completed integrated circuit devices are delivered to customers.
Device testing in a manufacturing environment can be a complex and expensive process. Due to the increasing complexity of integrated circuit devices, the devices can suffer from a wide range of faults, such as shorts or opens in the semiconductor and wiring layers, stuck-at faults, and so on. To facilitate the detection of each of these faults, each device is typically subjected to a large number of different test patterns, as a single test pattern may typically only cover certain types of faults. On the other hand, each test pattern that is run adds to the cost of the overall testing process of the devices.